Principal Memory Subsystem Architect
Core
Define AMD's multi-generation LPDDR and DRAM-buffer roadmap and lead technical positions for low-power DRAM and advanced memory-buffer technologies.
Role type
Principal Memory Subsystem Architect (Standards & Strategy)
Builds
Next-gen processors, AI systems, and memory subsystems for Client, Server, and Embedded markets
Domain
Semiconductor / Memory Technology / Standards Development
Required skills
LPDDR architecture, DRAM buffer design, JEDEC standards, system-level tradeoffs, cross-functional leadership, technical negotiation, consensus building, roadmap planning
Preferred skills
Master's degree or PhD in EE/CS, experience with DDR6, in-package buffers, firmware integration, security/attestation
Technologies
LPDDR, DDR6, JEDEC, SoC, PHY, PMIC, firmware, authentication, attestation
Responsibilities
Define multi-generation architecture strategy and adoption plans; represent AMD in JEDEC for standards development; define requirements for devices, buffers, and interfaces; coordinate system integration across controller, package, and firmware; align vendors and suppliers on roadmaps and interoperability; lead cross-functional workgroups and resolve technical tradeoffs
Seniority
Principal, strategy & mentorship
