RTL Methodology Silicon Design Engineer
Core
Build infrastructure, tooling, and AI-powered capabilities to multiply the efficiency and productivity of AMD's Core RTL team for next-generation CPU cores.
Role type
Senior IC RTL Methodology Engineer (AI/Tooling)
Builds
AI-powered tooling, agentic workflows, and static analysis ecosystems for RTL design
Domain
Semiconductor / CPU Design / Hardware Engineering
Deliverable
production ML models
Required skills
Verilog/SystemVerilog, Python, LLMs/Agentic frameworks, Static analysis, HDL parsers, Scripting (Perl/Shell/TCL)
Preferred skills
CPU architecture, Digital design workflows, AI tool quality evaluation
Technologies
Verible, Slang, Verilator, Surelog, LLMs, RAG
Responsibilities
Develop AI-powered tools and agentic workflows for RTL design; Own and advance the RTL static analysis ecosystem; Execute and refine methodology and tools for RTL design; Collaborate on engineering infrastructure for RTL development
Seniority
Senior, hands-on IC
