CPU RTL Design Engineer
Core
Design and optimize next-generation, high-performance CPU core pipeline logic and microarchitecture features for client, server, and AI platforms.
Role type
Senior IC CPU RTL Design Engineer
Builds
High-performance processor cores for AMD's client, server, and AI product lines
Domain
Semiconductor / CPU Architecture
Required skills
Verilog/SystemVerilog RTL development, modern CPU architecture (out-of-order), logic design, high-performance pipeline development, load/store/decode/execution subsystems, power-efficient design, synthesis, static timing analysis, Python/Tcl scripting
Preferred skills
Physical design concepts (DFT, clocking, reset), post-silicon debugging, cross-functional collaboration on PPA trade-offs
Technologies
Verilog, SystemVerilog, Python, Tcl
Responsibilities
Design RTL for CPU core pipeline components, contribute to microarchitecture definition, collaborate with verification and physical design teams, analyze PPA characteristics, support timing closure, resolve pre/post-silicon issues, develop scalable RTL methodologies
Seniority
Senior, hands-on IC
