Silicon Design Engineer
Core
Develop and deploy AI-driven automation workflows for next-generation semiconductor packaging design (substrates, interposers, bridge interconnects) to accelerate heterogeneous integration.
Role type
Senior IC automation engineer (packaging design & AI)
Builds
AI-driven design automation tools and workflows for 2.5D/3D packaging
Domain
Semiconductor manufacturing / Advanced packaging / EDA
Deliverable
production ML models
Required skills
Python, Tcl, SKILL, C++, AI/ML frameworks (PyTorch, TensorFlow), EDA packaging tools (Cadence APD/SiP, Siemens Xpedition, Synopsys 3DIC/Compiler), signal integrity optimization, auto-routing, component placement
Preferred skills
Design verification flows (DRC/LVS), electrical extraction, Cadence Allegro automation, PowerSI workflows, advanced packaging architectures (Chiplets, Fan-Out, Hybrid Bonding)
Technologies
PyTorch, TensorFlow, Python, Tcl, SKILL, C++, Cadence APD/SiP, Siemens Xpedition, Synopsys 3DIC/Compiler, PowerSI
Responsibilities
Develop AI workflows for substrate/interposer/bridge design; Optimize design stages (auto-routing, placement, SI); Evaluate next-gen EDA features for 2.5D/3D packaging; Build closed-loop optimization systems with analysis teams; Document automation efficiency gains and ROI.
Seniority
Senior, hands-on IC
