IOHUB Design Verification Engineer
Core
Define verification strategy and scope for AMD's IOHUB IP (PCI host bridge and IOMMU), develop test plans, implement DRVR, and drive verification closure for high-performance interconnects.
Role type
Senior IC design verification engineer (ASIC/SoC)
Builds
High-performance interconnect IP for discrete GPUs, ML products, APUs, servers, and game consoles
Domain
Semiconductor hardware design verification
Required skills
UVM, Verilog, SystemC, SystemVerilog, coverage-based verification, hardware assertions (PSL/SVA), constrained-random techniques, verification planning, virtualization knowledge
Preferred skills
Experience with complex IP/ASIC/SoC verification, CPU/GPU/PCIe/HT experience, AI assistant development, global company experience
Technologies
UVM, Verilog, SystemC, SystemVerilog, PCIe, HT, DRVR, PSL, SVA
Responsibilities
Define IOHUB verification strategy and scope; Develop IOHUB test plan and implement DRVR; Collaborate with Design/Architecture teams on verification components; Attend global conference calls for strategy alignment
Seniority
Senior, hands-on IC
