Post Silicon High-Speed I/O Validation Engineer
Core
Develop and execute validation test plans, infrastructure, and debug strategies for high-speed IO features (UCIe, UALink, PCIe, CXL) in AMD datacenter CPUs.
Role type
Senior IC validation engineer (high-speed IO)
Builds
Datacenter CPU server products
Domain
Semiconductor / High-speed interface protocols
Required skills
High-speed IO protocol expertise (UCIe, UALink, PCIe Gen5/6+, CXL), SoC validation, post-silicon debug, test plan development, root-cause analysis, scripting (C/C++, Python, Perl), lab equipment operation (oscilloscopes, logic analyzers), system architecture knowledge
Preferred skills
Leadership in SoC design/validation, silicon bring-up experience, multi-project execution, board/platform-level debug, industry consortium participation
Technologies
UCIe, UALink, PCIe, CXL, Linux, Windows, C/C++, Python, Perl, Oscilloscopes, Logic Analyzers
Responsibilities
Develop feature enablement and validation test plans for SoC and system-level features, create test content for focus and stress testing, build post-silicon validation infrastructure, debug SoC issues and drive root-cause analysis, collaborate on validation tools and strategies, lead internal task forces and industry consortiums
Seniority
Senior, hands-on IC
