CPU Microarchitecture & Cache RTL Design Engineer
Core
Design and implement high-performance, energy-efficient cache and routing fabric solutions for AMD's next-generation CPU cores.
Role type
Senior IC VLSI RTL Design Engineer (CPU Microarchitecture)
Builds
CPU cores, caches, and chiplet technologies for server, client, and gaming products
Domain
Semiconductor / CPU Microarchitecture
Required skills
Cache architecture design, Cache Controller RTL, Cache Array RTL, CPU Coherency, Coherent NoC, Cache Allocation/Replacement Policy, Digital RTL Design, Verilog HDL, Scripting
Preferred skills
Cache Controller and Array RTL implementation, CPU Coherency, Coherent NoC, Cache Allocation and Replacement Policy, Quality of Service, Fairness, Forward Progress architecture
Technologies
Verilog HDL
Responsibilities
Collaborate with Cache and CPU Architects to design optimized high-performance Cache and Routing Fabric designs; Collaborate with Physical Design teams to develop RTL optimized for physical implementation and timing closure; Collaborate with Design Verification teams to develop verifiable architectures and features; Collaborate with Design for Test teams to develop reliable and testable RTL; Work across global teams to solve complex architectural interactions between IP and SoC designs; Guide and mentor other engineers
Seniority
Senior, hands-on IC with mentorship responsibilities
