Power Analysis and Optimization Engineer
Core
Technical engineer optimizing datacenter server SoC power management features, performing power characterization, and defining product specifications.
Role type
Senior IC hardware engineer (power management)
Builds
Datacenter server SoC power management features and optimized product definitions
Domain
Semiconductor / Computer Hardware / Datacenter
Required skills
SoC validation and debug, power management feature enablement and optimization, hardware architecture (CPU/APU, x86, PCIe, memory, bus logic), software architecture (driver, BIOS, firmware), manufacturing binning strategy, validation methodologies development, C/C++/Python/Perl scripting, Linux/Windows Server OS knowledge
Preferred skills
Lab equipment operation (NIDAQ, oscilloscopes, logic analyzers, protocol analyzers), multi-tasking
Technologies
x86 microprocessors, Server platforms, C, C++, Python, Perl, Linux, Windows Server, NIDAQ, oscilloscopes, logic analyzers, protocol analyzers
Responsibilities
Interface with silicon, power architect, firmware and platform teams to close power management feature evaluation in pre-silicon phase; Develop test plans for post silicon power management feature tuning and power characterization; Post silicon power management feature tuning to optimize power and performance; Post silicon power characterization and correlation; Optimize and finalize fuse recipe with manufacturing team to lock product definition
Seniority
Senior, hands-on IC
