Principal Memory Sub-System Validation Lead
Core
Lead pre- and post-silicon validation and characterization of on-die High-Bandwidth Memory (HBM) for AMD's Datacenter GPU (Machine Instinct product) to ensure delivery of industry-leading Datacenter solutions for Machine Learning (ML) and High-Performance Computing (HPC).
Role type
Principal, hands-on IC validation lead
Builds
Datacenter GPU memory subsystems for ML and HPC
Domain
Semiconductor hardware, High-Bandwidth Memory (HBM), Datacenter
Required skills
HBM subsystem validation, SoC memory architecture, Unified Memory controller, PHY design, high-speed IO interface, DRAM device calibration, PVT Shmoo Characterization, JTAG/I2C/Tester/Lab tools, C/C++/Python programming, Linux/Windows platforms
Preferred skills
DDR/LPDDR validation, post-silicon debug, cross-functional collaboration, DRAM vendor experience, ML/HPC test case development
Technologies
HBM, DDR, LPDDR, JTAG, I2C, Linux, Windows, C, C++, Python
Responsibilities
Develop and execute test plans for HBM Functional and Electrical Validation, drive debug of post-production issues and customer returns, mentor junior engineers, collaborate with Design, Verification, and Software teams
Seniority
Principal, hands-on IC
