2027 PhD SerDes Optical Transceivers Silicon Design and Architecture Modeling Engineer Intern/Co-op
Core
PhD intern designing and modeling silicon architecture for high-speed SerDes optical transceivers.
Role type
PhD intern, silicon design and architecture modeling
Builds
Next-gen optical transceiver silicon designs and architecture models
Domain
Semiconductor, high-speed interconnects, optical communications
Required skills
device physics, circuit design, RTL/logic design, design automation, RF design, DAC design, ADC design, SerDes design, DSP design, CDR design, PLL design, clocking circuit design
Preferred skills
simulation, modeling, or design tools for validation
Technologies
CAD, AI, software development, modeling environments
Responsibilities
Define objectives and explore solutions for design problems, research and evaluate innovative solutions using analytical and simulation-based approaches, document technical findings and deliver final presentations
Seniority
PhD student, research-focused
