Lead IP Verification Engineer
Core
Architect and implement UVM verification environments for next-generation PCIe and CXL-based FPGA and ASIC solutions.
Role type
Lead IP Verification Engineer
Builds
FPGA and ASIC IP solutions for PCIe and CXL
Domain
Semiconductor / Hardware Verification
Required skills
UVM methodology, SystemVerilog, Verilog, high-speed protocol verification (PCIe, CXL, Ethernet), Python/Perl scripting, verification automation, regression testing, debug, technical leadership
Preferred skills
ASIC/FPGA lifecycle experience, performance verification, simulation optimization, HLS tools, AI-assisted verification, mentoring
Technologies
UVM, SystemVerilog, Verilog, PCIe, CXL, Ethernet, Python, Perl, HLS
Responsibilities
Architect and implement IP or subsystem-level UVM verification environments; Collaborate with architects, hardware designers, and firmware teams to define and verify new features; Develop comprehensive verification plans; Develop directed and constrained-random tests and execute regressions; Drive verification automation and methodology improvements
Seniority
Senior, hands-on IC with leadership
