Functional Verification Lead (Memory Subsystem)
Core
Provide technical leadership and contribute to high-speed Memory Controller IP Verification for DDR5/6, UCIe, HBM, and LPDDR designs.
Role type
Senior IC verification lead (memory subsystem)
Builds
Functional correctness of high-performance memory controller IPs and SoC designs
Domain
Semiconductor / High-performance computing / Memory subsystems
Required skills
UVM/OVM, System Verilog, Verilog, simulation environments, formal verification, memory controller protocols, board skew/jitter modeling, verification strategy, team leadership
Preferred skills
Verification architecture, assertion-based verification, metric-driven verification, formal property checking tools, gate-level simulation, power verification, silicon debug
Technologies
Synopsys VCS, Cadence IES, Cadence Jasper, Synopsys
Responsibilities
Design and develop simulation/formal verification environments at block and SoC level, drive verification strategies and execution, lead teams of 9+ engineers, ensure verification closure and delivery to programs
Seniority
Senior, hands-on IC with leadership
