2026 Graduate Trainee - Product Development Engineer Signal Integrity (December Intake)
Core
Define, model, analyze, and verify signal integrity specifications for AMD server products from die to board level.
Role type
Graduate Trainee, Signal Integrity Design Engineer
Builds
Next-generation AMD server products (DDR5, PCIe5, USB-4, CXL, xGMI)
Domain
Semiconductor hardware engineering, high-speed digital logic, server infrastructure
Required skills
Electromagnetic modeling, post-silicon measurement correlation, channel optimization, power delivery network simulation, system-level signal integrity simulation, high-speed board design, analog simulation, 3-D modeling, measurement techniques
Preferred skills
Transmission line theory, low-voltage swing signaling, I/O driver/receiver modeling, IBIS-like modeling, PCIeX Physical layer, LPDDR4/5, 100+Gig interfaces, Silicon or board design experience
Technologies
ANSYS HFSS/Q3D, ANSYS SIWAVE, Seasim, S2eye, Hspice, ADS, DSO, TDR, VNA, ParBERT
Responsibilities
Electromagnetic modeling of 3-D structures including vias, connectors, and sockets; Verify and correlate post-silicon measurement against spec; Deliver channel optimization and model creation; Perform board/system-level power delivery network AC+DC simulation; Simulate system-level signal integrity for future DDR5 memory bus and high-speed SERDES links; Resolve challenges in high-speed board design, power, and analog areas
Seniority
Graduate Trainee, entry-level IC
