CareerPlan

Senior Chip Lead Engineer-SoC/ASIC

San Jose, CaliforniaFull-time2026-09-03 → 2026-10-22
No visa sponsorship

Core

Lead full-chip programs from architectural concept through production shipment, serving as a technical partner to chip leads across cross-functional teams.

Role type

Senior IC chip lead engineer (SoC/ASIC)

Builds

Next-generation processors, AI accelerators, and leading-edge silicon products

Domain

Semiconductor industry, SoC/ASIC design, FPGA

Required skills

SoC and subsystem architecture, RTL design and synthesis, verification methodologies, physical design principles, timing closure, power optimization, manufacturing test and DFT, silicon bring-up and debug, Verilog/VHDL/SystemVerilog, EDA tools, semiconductor manufacturing processes

Preferred skills

Advanced process nodes (7nm and below), multiple chip architectures (CPU, GPU, FPGA, AI/ML accelerators), ASIC and FPGA development background, customer/vendor/foundry interaction, technical leadership and mentoring

Technologies

Verilog, VHDL, SystemVerilog, EDA tools

Responsibilities

Lead chip design initiatives from architectural concept through production release, provide technical guidance across all phases of the chip development lifecycle, drive technical decisions in ambiguous environments, partner with chip leads and program managers for scheduling and risk mitigation, interface with customers, foundries, IP vendors, and EDA tool suppliers, identify and resolve complex technical challenges throughout the design flow

Seniority

Senior, hands-on IC with program ownership