Gate Level Design Verification
Core
Gate-level validation of next-generation, high-performance x86 processors and related IP, focusing on post-synthesis verification, low-power validation, simulation, debugging, and automation.
Role type
IC digital design verification engineer
Builds
High-performance microprocessor designs and related IP
Domain
Semiconductor / Computer Architecture
Required skills
Verilog, SystemVerilog, VCS, ModelSim, Python, Shell, Perl, Ruby, Unix/Linux, Git, Perforce, digital logic, computer architecture, microprocessor design
Preferred skills
x86 architecture, automation tool development
Technologies
VCS, ModelSim, Python, Shell, Perl, Ruby, Git, Perforce
Responsibilities
Run gate-level simulations, analyze results, and assist with debugging functional and design issues; Support gate-level low-power verification and netlist validation activities; Develop and maintain scripts and automation tools used in gate-level build and simulation flows; Verify design behavior against relevant architectural and design specifications; Create and maintain verification documentation, including test plans, testbench information, and methodology guidelines; Participate in technical reviews and share verification findings with peers and relevant stakeholders.
Seniority
Mid-level, hands-on IC
