Verification Engineer
Core
Lead and contribute to the verification of Network on Chip (NOC) IPs and Subsystems to prove functional correctness of SOC designs.
Role type
Senior IC verification engineer (digital design)
Builds
Network-on-Chip (NOC) IPs, subsystems, and SOC designs
Domain
Semiconductor / VLSI / Digital Design
Required skills
System Verilog, UVM, ASIC/SoC verification methodologies, constraint-random verification, coverage-driven verification, formal verification (SVA), debugging complex digital designs, coverage analysis
Preferred skills
NOC architecture verification, AXI3/4/DDR4/5/HBM/PCIe protocol verification, verification architecture, gate-level simulation, power verification, formal property checking tools (Cadence IEV, Jasper, Synopsys VC-Formal)
Technologies
System Verilog, UVM, Synopsys VCS, Cadence IES, Synopsys VC-Formal, Magellan, Cadence IEV, Jasper, AXI3/4, DDR4/5, HBM, PCIe
Responsibilities
Lead and plan verification of complex digital design blocks, create comprehensive verification test plans, design and architect testbenches in System Verilog and UVM, create and enhance constrained-random and/or directed verification environments, debug tests with design engineers, identify and write coverage measures, perform coverage analysis to achieve closure
Seniority
Senior, hands-on IC
