Senior DV methodologies & infrastructure
Core
Design Verification Infrastructure and Architecture for GPU ASICs, managing testbench environments, simulation configurations, and verification flows for System-On-Chip designs.
Role type
Senior IC Design Verification Infrastructure Engineer
Builds
Testbench environments, simulation flows, and verification infrastructure for high-performance GPUs
Domain
Semiconductor / ASIC Design Verification
Required skills
C/C++, UVM, Verilog/SystemVerilog, SOC architecture, digital system design, Perl/MySQL/PHP scripting, simulation debugging, test regression management
Preferred skills
Gate-level simulation, 3rd party tool evaluation, fast initialization sequence development
Technologies
UVM, Verilog, SystemVerilog, Perl, MySQL, PHP, C, C++
Responsibilities
Scoping testbench architecture and simulation configuration; developing fast initialization sequences for SOCs; supporting test regression flows; debugging simulation testcases and models; reviewing tools to improve simulation performance; collaborating with IP and SOC teams across global sites
Seniority
Senior, hands-on IC
