Sr. Staff Design Verification Engineer
Core
Design and implement RTL for complex digital and mixed-signal blocks, support physical design activities, and collaborate with verification teams for block-level verification in FPGA and ASIC/SoC development.
Role type
Sr. Staff IC RTL Design Engineer (FPGA/ASIC)
Builds
Next-gen FPGA and ASIC/SoC devices for Adaptive & Embedded Computing Group (AECG)
Domain
Semiconductor / VLSI / Digital Design
Required skills
RTL design (Verilog, SystemVerilog), Physical Design (Synthesis, DFT, Place-and-Route, STA), EDA tools (Synopsys, Cadence), UVM/OVM verification, Scripting (Perl, Tcl, Shell, Python), High-speed interfaces (HBM, SerDes, PCIe)
Preferred skills
FPGA architecture knowledge, Mentorship, Cross-functional collaboration, Complex IP integration
Technologies
Verilog, SystemVerilog, UVM, OVM, Perl, Tcl, Shell, Python, Synopsys DFT Compiler, TestMAX, PrimeTime, VCS, Cadence
Responsibilities
Design RTL for complex digital/mixed-signal blocks, Support physical design (synthesis, DFT, place-and-route, STA), Collaborate with verification teams on block-level verification, Develop design automation flows using scripting languages, Partner with cross-functional teams to resolve technical issues
Seniority
Sr. Staff, hands-on IC with technical leadership
