Sr. Staff ASIC Design Engineer
Core
Design and implement RTL for complex digital and mixed-signal blocks, supporting physical design activities and verification for FPGA and ASIC products.
Role type
Senior IC ASIC/FPGA Design Engineer
Builds
FPGA and ASIC devices for Adaptive & Embedded Computing Group (AECG)
Domain
Semiconductor / VLSI / Digital IC Design
Required skills
RTL design (Verilog, System Verilog), Physical Design (synthesis, place & route, STA), VLSI/IC design, EDA tools, Scripting (Perl, Tcl, Shell, Python), UVM/OVM, Mixed-signal design
Preferred skills
HBM, D2D, Serdes, PCIe protocols, FPGA architecture knowledge, Simulation/debug environments
Technologies
Synopsys DC Compiler, Primetime, VCS, Cadence Virtuoso, Perl, Tcl, Shell, Python, UVM, OVM
Responsibilities
Design RTL for digital/mixed-signal blocks, Support physical design (synthesis, DFT, place-and-route, STA), Collaborate on block-level verification using constrained-random/directed tests, Maintain and develop design automation flows, Partner with cross-functional teams
Seniority
Senior, hands-on IC
