Sr. Silicon Design Engineer
Core
Designing synthesizable RTL for high-performance IP cores targeting networking, security, storage, and communications applications.
Role type
Senior IC silicon design engineer (RTL/ASIC)
Builds
IP cores for high-performance AMD products
Domain
Semiconductor / ASIC design / Data communications
Required skills
Verilog/SystemVerilog RTL coding, ASIC architecture, EDA design flows, data networking protocols, synthesis and timing closure, functional verification, Python/TCL scripting
Preferred skills
AI-powered RTL design tools (Copilot, Cursor), LEC/CDC/lint execution, optical communications, encryption protocols (MACsec/IPsec), mentorship
Technologies
Verilog, SystemVerilog, Synopsys, Cadence, Siemens (Mentor), VS Code, GitHub Copilot, Cursor, Python, Perl, TCL, Makefile, bash
Responsibilities
Develop synthesizable RTL for IP cores, utilize AI tools for code generation and refactoring, collaborate with IP Architecture/Verification/SoC teams, resolve simulation regression failures, provide synthesis and timing closure support, mentor junior designers
Seniority
Senior, hands-on IC
