RTL Design & Integration Engineer
Core
Build early-stage RTL designs and AI-driven infrastructure for FPGA product development, supporting silicon implementation and IP integration.
Role type
Senior RTL Design & Integration Engineer (FPGA)
Builds
FPGA devices and silicon implementations for Adaptive & Embedded Computing Group (AECG)
Domain
Semiconductor / FPGA / Digital Design
Required skills
RTL design (Verilog/SystemVerilog), VLSI design flow, Physical Implementation (floorplanning, synthesis, P&R, STA), EDA tools (Synopsys, Cadence), UVM/OVM verification, Scripting (Perl, Tcl, Python, Shell)
Preferred skills
FPGA architecture knowledge, Digital/analog block implementation experience
Technologies
Verilog, SystemVerilog, Synopsys Design Compiler, Synopsys Primetime, Synopsys VCS, Cadence Virtuoso, UVM, OVM, Perl, Tcl, Python, Shell
Responsibilities
Collaborate with architects and SW-FW engineers to define product requirements and IP features; Build early-stage RTL designs driving Silicon and Solution co-development; Build and enhance AI-driven infrastructure to accelerate IP integration; Apply data-driven methodologies to align engineering teams; Support functional simulation and software quality checks; Partner with global teams for seamless integration and delivery.
