IP Verification Engineer
Core
Develop and execute verification strategies for PCIe, CXL, and NVMe IP architectures to ensure first-pass silicon success in FPGA and ASIC designs.
Role type
Senior IC ASIC verification engineer (IP level)
Builds
High-performance FPGA and ASIC chips for supercomputing, cloud, and AI applications
Domain
Semiconductor hardware design and verification
Required skills
UVM, System Verilog, Verilog, PCIe/CXL/NVMe/ethernet protocols, directed and random test generation, regression debugging, Python/Perl scripting, computer architecture knowledge
Preferred skills
Leadership/mentorship experience, simulation profile optimization, HLS tools/process, generative AI for test generation
Technologies
UVM, System Verilog, Verilog, PCIe, CXL, NVMe, Ethernet, Python, Perl, HLS tools
Responsibilities
Collaborate with architects and firmware engineers to define verification features for PCIe CXL IP; Develop test plans covering hardware, firmware, and software interactions; Code UVM-based testbenches and verification components; Build directed and random verification tests; Run regressions and debug failures to ensure functional and performance quality
Seniority
Senior, hands-on IC
