Principal Staff Silicon Design Engineer - DDR Verification
Core
Lead verification efforts for DDR interfaces (DFI, DDR5, LPDDR5) in high-performance server memory products, ensuring alignment between hardware, firmware, BIOS, and software.
Role type
Principal Staff Silicon Design Engineer (DDR Verification)
Builds
Server memory products (DIMMs) with advanced DDR protocols
Domain
Semiconductor / High-Performance Computing / Server Memory
Required skills
SystemVerilog, UVM, C/C++, Python, Perl, Formal Verification, DFT flows, GLS/NLP/XPROP simulation, Architecture analysis, Cross-functional collaboration
Preferred skills
VIP/BFM development from scratch, Mentorship, Technical publications/presentations, Pre-Si/Post-Si bug resolution
Technologies
SystemVerilog, UVM, Python, Perl, GLS, NLP, XPROP
Responsibilities
Lead verification strategy for DDR5/LPDDR5/DFI systems; Comprehend SOC including HW/FW/BIOS/SW alignment; Work with architects on technical risks and solutions; Contribute to verification methodology; Manage architecture analysis for feature changes; Collaborate on timing, emulation, and sign-offs; Support post-Si debugging
Seniority
Principal Staff, Technical Lead & Mentorship
