SOC Design verification engineer
Core
Plan, build, and execute pre-silicon verification for full chip, blocks, multi-chip, and system-level designs to ensure no bugs in the final design.
Role type
Senior IC SOC Design Verification Engineer
Builds
Verified processor architectures and system-level designs
Domain
Semiconductor / ASIC Design
Required skills
ASIC design verification, UVM testbenches, Verilog, System Verilog, C, C++, SystemC, functional simulation debugging, test plan development, coverage analysis, Perl, Python, shell scripting
Preferred skills
Hardware security features verification, SoC level boot flow, leadership or mentorship, HLS tools/process, simulation efficiency improvement
Technologies
UVM, Verilog, System Verilog, C, C++, SystemC, Perl, Python, Makefile, Linux, Windows
Responsibilities
Collaborate with architects, hardware, and firmware engineers to understand new features; Build test plan documentation; Estimate time for test development; Build directed and random verification tests; Debug test failures and resolve design defects; Review functional and code coverage metrics
Seniority
Senior, hands-on IC
