ASIC TOP Floorplan Intern, 2027
Core
Design and optimize floorplans for next-generation GPUs and SoCs during early chip development.
Role type
ASIC Floorplan Design Engineer (Intern)
Builds
High-performance GPUs and System-on-Chip (SoC) architectures
Domain
Semiconductor / Hardware Design
Deliverable
production ML models
Required skills
Verilog, System Verilog, Python, Perl, C/C++, CAD tools, physical design methodologies, chip floorplanning, power/clock distribution, packaging, place-and-route (P&R), timing closure
Preferred skills
Large-scale ASIC floorplan development experience
