SRAM Design Engineer
Core
Designing embedded SRAM macros at the transistor level, developing automated SRAM compilers, and guiding SOC design partners to achieve performance and cost goals.
Role type
Senior IC SRAM circuit designer and compiler developer
Builds
SRAM macros and automated compiler tools for NVIDIA SoCs
Domain
Semiconductor / Analog IC Design
Required skills
Transistor-level circuit design, SRAM macro design, layout implementation, physical and logical verification, debugging, CAD tools (Cadence Virtuoso), AI tool usage
Preferred skills
Silicon testing and debugging, advanced process node exploration, AI coding and analysis tools (Codex, Claude Code)
Technologies
Cadence Virtuoso, NVIDIA compute resources
Responsibilities
Design transistor-level SRAM circuits, supervise layout implementation, develop SRAM compilers for automated macro assembly, collaborate with SOC design partners on performance and cost optimization, guide silicon test and characterization efforts
Seniority
Senior, hands-on IC
