Senior Silicon Validation Methodology Engineer
Core
Define and own clocking and High-Speed I/O (HSIO) functional validation methodology for GPU/SOC/CPU products from specification through silicon bring-up.
Role type
Senior Silicon Validation Methodology Engineer (Clocking & HSIO)
Builds
Executable test content, pass/fail criteria, and bring-up plans for clocking and HSIO functionality.
Domain
Semiconductor / High-Speed Interconnects
Required skills
Silicon validation methodology, Clocking architecture, HSIO protocols (PCIe, CXL, USB, UFS, MGBE), SerDes, Signal Integrity (SI), Power Integrity (PI), Test strategy definition, Cross-functional collaboration, Debugging silicon failures, AI-enabled analysis
Preferred skills
Novel methodology creation, Open-source tool contributions, High-speed communication protocol trends
Technologies
PCIe, CXL, USB, UFS, MGBE, SerDes, SI/PI tools
Responsibilities
Define validation methodology from spec to silicon bring-up; Create executable test content and bring-up plans; Drive cross-functional alignment on validation strategy; Develop automated tools and scripts for validation efficiency; Debug silicon HSIO and clocking issues.
