VLSI Timing Methodology Intern - Summer 2027
Core
Research and develop compact device and system models to predict silicon timing behavior, using Machine Learning to speed up characterization and improve performance/reliability predictions.
Role type
VLSI Timing Methodology Intern
Builds
Large scale internal CAD tools and silicon projection methodologies
Domain
Semiconductor / VLSI / AI
Deliverable
production ML models
Required skills
Static Timing Analysis, MOSFET device physics, VLSI backend design, Machine Learning, Python/Perl/Tcl scripting
Preferred skills
BSIM or other device compact models, prior VLSI internship experience, VLSI Design or CAD Design coursework
