CareerPlan

Chip Design Verification Engineer

Israel, Tel AvivFull-time2026-08-20 → 2026-11-10

Core

Build reference models, verify, and simulate performance and power management related IPs for next-generation devices.

Role type

Chip Design Verification Engineer

Builds

Performance and power management IPs

Domain

Semiconductor / Chip Design

Required skills

RTL Verification, System-Verilog, UVM, Simulation

Preferred skills

System-Verilog UVM

Technologies

System-Verilog, UVM

Responsibilities

Build reference models, verify and simulate according to specifications and performance requirements, collaborate with Architecture and Design teams

Seniority

Mid-level, hands-on IC