Senior ASIC Power Management Micro Architect, Chip Design
Core
Designing and enabling Power Management IP blocks for NVIDIA's ASICs, from micro-architecture definition through post-silicon bring-up.
Role type
Senior ASIC Design Engineer (Power Management IP)
Builds
Power Management IP blocks for NVIDIA's product lines
Domain
Semiconductor / ASIC Design
Required skills
RTL design, front-end micro-architecture, full IP/ASIC design flow, post-silicon bring-up, low-power design techniques
Preferred skills
Power Management IP expertise, new technology development, post-silicon validation and debug
Technologies
RTL, ASIC design flow
Responsibilities
Own front-end micro-architecture and design of Power Management IP blocks; Deliver high-quality, synthesizable RTL; Partner with architecture, verification, physical design, and validation teams; Lead post-silicon debug, characterization, and enablement activities
Seniority
Senior, hands-on IC
