NVIDIA 2027 Internships: Hardware Design for Test (DFT)
Core
12-week full-time internship focusing on Hardware Design for Test (DFT) to ensure chip functionality and performance.
Role type
Hardware Design for Test (DFT) Intern
Builds
Chips and semiconductor products
Domain
Semiconductor / Hardware Engineering
Required skills
Design for Test (DFT), Digital Design, Test Architecture, Static Timing Analysis (STA), Debugging, Scan Chain Design, ATPG, Boundary Scan, Memory BIST, Logic BIST, Compression, At-Speed Testing, Delay Testing
Preferred skills
Perl, TCL, C, C++, Python, Synopsys, TetraMAX, Cadence Modus, Linux
Responsibilities
Design and implement DFT strategies, perform static timing analysis, debug pre-silicon and post-silicon issues, develop test architectures, verify chip operation at rated frequency.
Seniority
Intern
