Senior ASIC Design Verification Infrastructure and Tools Engineer – GPU
Core
Build and improve high-speed IO integration, build, simulation, and pre-submit qualification flows for large ASIC IP development, focusing on CI reliability, automation, and efficiency.
Role type
Senior IC ASIC Design Verification Infrastructure and Tools Engineer
Builds
High-speed IO integration, build, simulation, and pre-submit qualification flows for large ASIC IP
Domain
Semiconductor / ASIC Design / High-speed IO
Deliverable
infrastructure
Required skills
ASIC development workflows, UVM verification methodology, Verilog/SystemVerilog, Python/Perl scripting, root-cause analysis, distributed compute environments, CI/CD automation, engineering metrics
Preferred skills
AI workflow application, cross-domain system understanding, multi-project SoC experience
Technologies
VCS, Verdi, Xcelium, SystemVerilog, Python, Perl
Responsibilities
Apply practical AI workflows for debug assistance, run triage, summarization, and automation; Build and improve high-speed IO integration, build, simulation, and pre-submit qualification flows; Improve CI reliability, turnaround time, debuggability, and scalability across distributed compute environments; Root-cause complex failures across development, verification, build systems, tools, and compute environments; Turn recurring integration or qualification difficulties into durable automation and process improvements; Define, publish, and actively use metrics for integration latency, flow health, failure trends, and engineering efficiency; Collaborate with ASIC designers, verification engineers, firmware engineers, and infrastructure partners.
