SOC Clocks RTL Design Engineer
Core
Own the SOC clocking logic end-to-end for next-generation networking chips, translating micro-architecture specs into synthesizable RTL and driving it to silicon.
Role type
Senior IC RTL Design Engineer (Clocking)
Builds
SOC clock generation, distribution, and control logic (PLL integration, muxing, dividers, CDC infrastructure)
Domain
Semiconductor / SoC Design
Required skills
Verilog/SystemVerilog, Synthesis, Timing analysis, Clock gating, Clock muxing, Clock domain crossing (CDC), Reset synchronization, Physical Design collaboration
Preferred skills
PLL/clock generator integration, Clock tree constraint development, SOC-level clocking architecture ownership, Automation flow development
Technologies
Verilog, SystemVerilog, Lint tools, CDC/RDC tools, Formal verification tools, Synthesis tools
Responsibilities
Write synthesizable RTL for clock generation, distribution, and control; Define SOC clock and reset architecture; Own clock domain crossing (CDC) closure; Partner with micro-architecture on design intent and implementation cost; Collaborate with Physical Design on clock tree implementation and constraints; Support software teams on clock programming sequences and DVFS; Drive design quality via lint, CDC/RDC, and formal checks; Develop automation flows for RTL integration and quality checking.
Seniority
Senior, hands-on IC
