Senior Verification Engineer
Core
Develop and drive testplans, build scalable UVM-based infrastructure, and own verification sign-off for GPU and SoC display engines.
Role type
Senior IC verification engineer (display protocols)
Builds
High-quality display IPs for consumer, professional, automotive, and AI markets
Domain
Semiconductor hardware design (GPU/SoC) and display protocols
Required skills
UVM, SystemVerilog, Verilog, Python, C/C++, constrained-random stimulus, functional coverage, assertion-based verification, EDA tools (VCS, Verdi/Debussy, GDB), display protocols (DisplayPort, HDMI, MIPI DSI/CSI), low-power features
Preferred skills
Pixel processing, ISO performance testing, HLS-based designs, MMU/SMMU behavior verification, architectural specification shaping
Technologies
UVM, SystemVerilog, Verilog, Python, C/C++, VCS, Verdi, Debussy, GDB, DisplayPort, HDMI, MIPI DSI, MIPI CSI
Responsibilities
Define verification scope and develop testplans; Develop UVM testbenches and checkers; Critically reason through architectural solutions; Collaborate globally to deploy verification flows and debug integration issues
Seniority
Senior, hands-on IC
