RTL Power Optimization Engineer – New College Grad 2026
Core
Develop AI-driven RTL and architecture power optimization solutions for next-generation GPUs and networking chips to improve product power efficiency.
Role type
Junior IC RTL Power Optimization Engineer
Builds
Pre-silicon power analysis tools, AI/ML-driven optimization flows, and power-efficient GPU/networking chip architectures
Domain
Semiconductor / AI Hardware / VLSI
Deliverable
production ML models
Required skills
RTL power optimization fundamentals, Python programming, Machine Learning, VLSI concepts, backend flows (logic synthesis, place-and-route), low-power design patterns (clock gating, power gating), power analysis tools (PowerArtist, PrimeTime PX), RTL debugging
Preferred skills
MS or PhD in Electrical/Computer Engineering, experience with AI/ML in EDA
Technologies
Verilog, Python, PowerArtist, PrimeTime PX
Responsibilities
Use internal and industry-standard tools for pre-silicon gate-level and RTL power analysis; Develop and share best practices for power analysis; Perform comparative power analysis to identify trends and anomalies; Collaborate with architects and designers to interpret power data and drive fixes; Select and run workloads for power analysis; Prototype architectural features in Verilog and analyze power
Seniority
Junior, entry-level (New College Grad 2026)
