Senior SoC Subsystem and I/O Architect - LPU
Core
Define high-level architecture for next-generation AI and high-performance computing products, specifically focusing on SoC subsystems and uncore IPs.
Role type
Senior SoC Subsystem and I/O Architect
Builds
Next-generation AI and high-performance computing products (GPUs, LPUs)
Domain
Semiconductor / SoC Architecture / AI Accelerators
Deliverable
production ML models
Required skills
SoC architecture, uncore subsystem development, IO and interconnect cores (PCIe, CXL, NVLink, UCIe, AXI, CHI, NoC), memory ordering and coherency, boot and reset architecture, firmware interfaces, functional/architectural modeling (C++, SystemC, Python), tradeoff analysis (bandwidth, latency, power, area, timing)
Preferred skills
LPU/GPU/CPU/AI accelerator/chiplet/multi-die SoC architecture, deep learning workloads understanding, post-silicon validation
Technologies
C++, SystemC, Python, PCIe, CXL, NVLink, NVLink-C2C, UCIe, AXI, CHI, NoC
Responsibilities
Define high-level SoC subsystem architecture; Convert product requirements into architectural specifications for uncore, IO, memory, and firmware-facing subsystems; Collaborate with IP teams to develop detailed build documents; Specify subsystem behavior including enumeration, configuration, and error handling; Build or guide functional and architectural models to validate architecture intent; Drive tradeoffs across performance, power, and security metrics; Review IP specifications and verification plans; Collaborate with architecture, IP, firmware, software, RTL, and verification teams.
Seniority
Senior, hands-on IC
