PCIe IP Verification Engineer
Hybrid
Core
Verify ASIC design, architecture, golden models, and micro-architecture of PCIe controllers at IP/sub-system levels using UVM.
Role type
Senior IC verification engineer (PCIe IP)
Builds
Reusable bus functional models, monitors, checkers, and scoreboards
Domain
Semiconductor / Hardware Verification / Interconnect Protocols
Required skills
UVM, SystemVerilog, Verilog, PCIe protocol knowledge, functional coverage, constrained random verification, ASIC design verification
Preferred skills
PCIe Gen3+, CXL system architecture, Perl/Python scripting, debugging
Technologies
UVM, SystemVerilog, Verilog, PCIe, CXL
Responsibilities
Define verification scope, develop test plans and infrastructure, verify design correctness, collaborate with architects and designers
Seniority
Senior, hands-on IC
