Senior Performance Modeling Architect, CPU Fabric and LLC
Core
Lead architectural definition and improvement of next-generation CPU Cache Hierarchies and interconnects for Automotive and Data Center systems.
Role type
Senior IC Performance Modeling Architect (CPU Fabric)
Builds
Scalable CPU cache hierarchies (L3/System Cache) and coherent fabrics
Domain
Semiconductor hardware design (CPU microarchitecture, memory systems)
Deliverable
production ML models
Required skills
Computer architecture, CPU microarchitecture, cache coherency protocols, C++, SystemC, Python, Network-on-Chip (NoC) topologies (via careerplan.io/jobs/893395031205-senior-performance-modeling-architect-cpu-fabric-and-llc-at-nvidia)
Preferred skills
Functional safety (ISO 26262), Performance Monitoring Unit (PMU) events, Formal verification, Custom tooling development, Advanced memory systems (CXL, HBM)
Responsibilities
Develop and maintain high-fidelity, cycle-accurate performance models for coherent interconnects and shared caches; Analyze performance bottlenecks across automotive SoCs and data center architectures; Evaluate performance impact of coherency protocols and snooping filters; Run industry-standard benchmarks to drive architectural trade-offs; Collaborate with build/verification teams to correlate models with silicon
Seniority
Senior, hands-on IC
