Senior Formal Verification Engineer - LPU
Core
Verify AI-related sophisticated ASIC designs and features using formal verification methods to ensure correctness and compliance with specifications.
Role type
Senior IC formal verification engineer (ASIC)
Builds
High-quality, formally verified ASIC designs for AI accelerators
Domain
Semiconductor hardware design (ASIC) + Formal verification
Deliverable
production ML models
Required skills
SystemVerilog Assertions (SVA), formal property verification, formal verification tools (JasperGold, VC Formal), scripting (Tcl, Python), ASIC verification methodologies
Preferred skills
Full-cycle formal sign-off experience, FPV apps, sequential equivalence checks, datapath verification, GPU/LPU architecture knowledge
Technologies
SystemVerilog, JasperGold, VC Formal, Tcl, Python
Responsibilities
Define verification scope and ensure correctness; employ formal techniques to acquire bounded proofs; collaborate with architects and designers to resolve deep design issues; develop advanced formal verification environments and automated flows; mentor junior engineers; support silicon bring-up and debug using formal methods
Seniority
Senior, hands-on IC
