EDA Workflow Optimization Engineer
Core
Optimize chip design workflows (inception through production) by building scalable infrastructure, debugging complex multi-discipline problems, and enabling engineers to develop at high speed.
Role type
Senior IC EDA Workflow Optimization Engineer
Builds
Scalable, reliable, high-performance systems and tools for chip development
Domain
Semiconductor / EDA / Chip Design
Deliverable
infrastructure
Required skills
UNIX systems programming, Python/Shell automation, EDA tools, ASIC/VLSI/CAD workflow knowledge, job schedulers (LSF/SLURM), C/C++/Perl, distributed systems, data analysis
Preferred skills
GPU-based workload management, architectural decision-making in storage/networking/compute
Technologies
UNIX, Python, Shell, C/C++, Perl, IBM Spectrum LSF, SLURM, GPU
Responsibilities
Investigate and debug complex multi-discipline problems in UNIX environments; Build metrics to measure flow performance; Work with chip engineers to optimize compute and storage usage; Participate in full life-cycle of tool development, test, and deployment; Continuously improve chip development process
Seniority
Senior, hands-on IC
