Senior ASIC Design Engineer - NOC IP
Core
Design state-of-the-art memory subsystem components for Graphics Processors, focusing on micro-architecture and RTL development.
Role type
Senior IC ASIC Design Engineer (Memory Subsystem)
Builds
Graphics Processor memory subsystems for consumer graphics, self-driving cars, and AI.
Domain
Semiconductor / Hardware Design
Required skills
RTL design, Verilog, ASIC design flow, micro-architecture, timing analysis, logic synthesis, DFT, verification, FPGA prototyping
Preferred skills
Memory subsystem or network interconnect IP experience, Python/Perl/shell scripting, team leadership
Technologies
VCS, Debussy, GDB, FPGA
Responsibilities
Own micro-architecture and RTL development of design modules; Micro-architect features to meet performance, power and area requirements; Work with HW architects to define critical features; Collaborate with verification teams to verify the correctness of implemented features; Co-operate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable; Interact with FPGA and S/W teams to prototype the design and ensure that S/W is tested; Work on post-silicon verification and debug.
Seniority
Senior, hands-on IC
