Lead Design Verification Engineer
Core
Architect, develop, and debug simulation and formal verification environments for Network-on-Chip (NOC) IPs, subsystems, and SoCs to prove functional correctness.
Role type
Senior IC design verification engineer (digital/SoC)
Builds
Verified digital logic blocks, subsystems, and full System-on-Chip (SoC) designs
Domain
Semiconductor / VLSI / Digital Design
Required skills
SystemVerilog, UVM, constrained-random verification, formal verification (SVA), coverage-driven verification, ASIC development lifecycle, regression management, Perl scripting, debugging complex digital designs
Preferred skills
NOC verification, AXI/PCIe/DDR protocols, gate-level/power verification, formal property checking tools (Cadence/IEV, Jasper, Synopsys/VC-Formal), verification architecture
Technologies
SystemVerilog, UVM, Synopsys VCS, Cadence IES, Cadence IEV, Jasper, Synopsys VC-Formal, Magellan, Perl
Responsibilities
Plan verification for complex digital design blocks; Design and architect testbenches in SystemVerilog and UVM; Create constrained-random and directed verification environments; Debug tests with design engineers; Identify and write coverage measures; Perform coverage analysis to achieve closure
Seniority
Senior, hands-on IC
