Fellow Architect, Functional & Performance Verification
Core
Lead the evolution of AMD's pre-silicon verification and validation strategy for IP, subsystem, and SoC development within the Adaptive and Embedded Computing Group.
Role type
Fellow-level Functional and Performance Verification Architect
Builds
Next-generation verification architectures, methodologies, and technologies for semiconductor designs
Domain
Semiconductor / Hardware Verification
Required skills
C/C++, Python, Perl, Ruby, Verilog, UVM, constrained-random verification, directed verification, coverage-driven verification, formal verification, power verification, performance verification, implementation verification, pre-silicon prototyping, emulation platforms, EDA tool strategy, technical mentorship, thought leadership
Preferred skills
Expertise in leading EDA vendor tools (Synopsys, Cadence, Siemens), strategic engagement with EDA vendors, publications/patents/presentations, cross-disciplinary collaboration
Technologies
UVM, Synopsys, Cadence, Siemens, emulation platforms, prototyping platforms
Responsibilities
Define and execute functional and performance verification strategies; Lead simulation-based verification methodologies (constrained-random, directed, coverage-driven); Advance formal, power, performance, and implementation verification; Lead firmware-based validation strategies on prototyping/emulation platforms; Influence verification methodologies with executive leadership; Partner with architecture/RTL teams to embed Design-for-Verification principles; Establish strategic engagements with EDA vendors; Mentor verification engineers; Contribute to technical leadership via publications and presentations
Seniority
Fellow, strategic vision & technical mentorship
