PCIe, CXL and Highspeed IO Validation Engineer
Core
Principal validation engineer developing and executing test plans, infrastructure, and debug strategies for high-speed IO interfaces (PCIe, CXL) in datacenter CPUs.
Role type
Principal validation engineer (post-silicon)
Builds
High-speed IO interfaces for AMD datacenter/server CPUs
Domain
Semiconductor / High-performance computing
Required skills
PCIe Gen5/6+ validation, CXL validation, SoC validation, system-level debug, root-cause analysis, validation infrastructure development, test plan creation, scripting (C/C++, Python, Perl), board/platform-level debug, protocol/logic analyzer usage, oscilloscope usage
Preferred skills
x86 microprocessor architecture knowledge, Server platform architecture knowledge, silicon bring-up experience, multi-project execution, Linux/Windows server OS knowledge
Technologies
PCIe, CXL, UCIe, C/C++, Python, Perl, Linux, Windows, Logic analyzers, Oscilloscopes
Responsibilities
Develop and execute feature enablement and validation test plans for SoC and system-level features; Develop test content for focus and system-level stress testing; Develop post-silicon validation infrastructure; Debug and drive root-cause analysis for SoC issues; Collaborate on tools to improve validation and debug; Improve post-silicon validation test strategy and process
Seniority
Principal, hands-on IC
