Senior Staff Front End Automation Engineer
Core
Senior Front-End Design Automation Engineer shaping and advancing front-end EDA flows (RTL lint, static timing analysis, constraints, RTL quality signoff) and modernizing them with AI/ML and agent-based automation.
Role type
Senior IC silicon design automation engineer
Builds
Front-end EDA flows for RTL lint, STA, constraints, and CDC/RDC signoff
Domain
Semiconductor / Silicon Design Automation
Deliverable
production ML models
Required skills
RTL lint/design-quality, static timing analysis (STA), constraints (SDC), CDC/RDC signoff, low-power (UPF), scripting (Tcl, Python, Perl), flow infrastructure (Jenkins), EDA tools (Synopsys, Cadence), AI/ML or LLM-based agents, FPGA/ASIC/SoC experience
Preferred skills
Technical roadmap architecture, user enablement, cross-functional partnership, Perforce/ICManage
Technologies
Jenkins, Perforce, ICManage, Synopsys, Cadence, Python, Tcl, Perl, AI/ML, LLM agents
Responsibilities
Shape technical direction and roadmap for front-end flows; Drive AI-based modernization for lint triage, timing debug, and regression analysis; Serve as technical resource and mentor for design teams; Drive user enablement and adoption of timing-flow and low-power methodologies; Partner with design, CAD, IP, and library teams to maintain regression/CI pipelines
