Principal Cache RTL Design - CPU Team
Core
Architecting and designing high-performance x86-core ISA features, cache, coherency, and power management for modern processors.
Role type
Principal IC RTL Design Engineer (CPU)
Builds
High-performance x86 CPU cores and subsystems
Domain
Semiconductor / CPU Design
Required skills
Verilog RTL design, x86 architecture, cache/coherency design, power management, IP integration, clock-domain crossing, low-power techniques, EDA tools, Python/Perl scripting
Preferred skills
Digital IP/ASIC design cycle, synthesis and timing closure, post-silicon validation, functional design verification, multi-scale project experience
Technologies
Verilog, Python, Perl, EDA tools
Responsibilities
Design high-performance x86-core ISA features and cache/coherency; Optimize RTL for power efficiency; Resolve inter-IP integration issues; Lead design team and mentor junior members; Collaborate with DFT, Physical Design, and SOC teams
Seniority
Principal, hands-on IC with mentorship
