Lead Verification Engineer - PCIE/CXL
Core
IP verification engineer developing testbenches and verification frameworks for PCIe/CXL based FPGA and ASIC designs.
Role type
Senior IC silicon verification engineer
Builds
FPGA and ASIC IP blocks for AI, data centers, PCs, gaming, and embedded systems
Domain
Semiconductor hardware design and verification
Required skills
UVM, System Verilog, Verilog, PCIe/CXL protocol knowledge, directed and random test generation, regression debugging, Python/Perl scripting
Preferred skills
ASIC verification lifecycle experience, leadership/mentorship, simulation efficiency optimization, HLS tools, generative AI for test generation
Technologies
UVM, System Verilog, Verilog, Python, Perl, PCIe, CXL
Responsibilities
Collaborate with architects and firmware engineers to define verification plans for PCIe/CXL features; Develop test plan documentation covering hardware, firmware, and software interactions; Code UVM-based testbenches, monitors, scoreboards, and checkers; Build directed and random verification tests; Run regressions and debug failures to ensure design quality
Seniority
Senior, hands-on IC
