Sr. Design Verification Engineer
Core
Design Verification Engineer developing UVM-based testbench architectures and driving verification closure for complex, high-performance ASIC designs in data center networking.
Role type
Senior IC Design Verification Engineer
Builds
High-performance DPU and software stack for data center networking
Domain
Semiconductor / Data Center Networking
Required skills
SystemVerilog, UVM, constrained-random verification, regression triage, root-cause debugging, simulation optimization, protocol verification (PCIe, AXI, Ethernet, DDR), scripting (Python/Tcl/Shell)
Preferred skills
Performance verification, power-aware verification (UPF), formal verification, FPGA/HAPS validation, architectural modeling, C/C++ reference models
Technologies
VCS, Verdi/DVE, Python, Tcl, Make, PCIe, AXI, Ethernet, DDR, DMA
Responsibilities
Develop UVM-based testbench architectures for IP, subsystem, and SoC levels; Create test plans, feature mappings, and coverage strategies; Execute verification plans and perform regression triage; Debug architectural, functional, and performance issues across RTL and interfaces; Optimize simulations and coverage closure; Mentor junior engineers and provide technical leadership
Seniority
Senior, hands-on IC
