Debug Validation Engineer — Multiple Levels
Core
Lead post-silicon debugging and validation for next-generation AI compute silicon and systems, identifying and resolving complex hardware, firmware, and system-level issues during bring-up and characterization.
Role type
Senior IC Debug Validation Engineer (AI Compute Silicon)
Builds
AI compute silicon and platform technologies for Graphcore's AI ecosystem
Domain
Semiconductor hardware engineering / AI compute stack
Deliverable
production ML models
Required skills
Post-silicon debug methodologies, SoC and platform architecture expertise, bare metal environment experience, Python and C programming, Linux proficiency, JTAG/scan/DFT infrastructure knowledge, fault tree analysis, root cause analysis, automated debug infrastructure development
Preferred skills
PCIe/Ethernet/Memory driver experience, CoreSight debug infrastructure usage, Arm CPU architecture knowledge, AMBA protocols, mixed-signal component understanding, ML workload characterization
Technologies
Python, C, JTAG, DFT, CoreSight, PCIe, Ethernet, LPDDR, DDR, HBM, I2C, I3C, SPI, Arm, AMBA
Responsibilities
Lead post-silicon debugging and validation efforts, analyze logs and telemetry to isolate system failures, develop automated debug and regression infrastructure, collaborate with architecture and firmware teams to determine root causes, define validation metrics and reporting standards, support silicon readiness reviews
Seniority
Senior, hands-on IC
