RTL Tools & Methodology Engineer
Based in United StatesNo visa sponsorship
Core
Develop and improve front-end design and static verification flows (Lint, CDC, formal equivalence, low-power) to ensure high-quality RTL design for next-generation FPGA products.
Role type
Hardware Development Engineer (RTL Design Methodology)
Builds
Front-end design and static verification flows for FPGA silicon
Domain
Semiconductor / Hardware Design
Required skills
RTL design (SystemVerilog, Verilog, VHDL), static verification, Perl, Python, TCL
Preferred skills
Master's or PhD in Electrical/Computer Engineering
Technologies
SystemVerilog, Verilog, VHDL, Perl, Python, TCL
Responsibilities
Collaborate with design teams to drive continuous improvements in front-end design methodologies; Support deployment of static verification flows; Leverage corporate AI systems to streamline workflows.
Seniority
Early-career, hands-on IC
